1. Field of the Invention
The present invention relates generally to a computer-aided wiring graphic verification method, program and apparatus for verifying wiring graphic data for wiring masks created from layout data for circuit design of a large-scale semiconductor integrated circuit, etc., and more particularly to a wiring graphic verification method, program and apparatus for verifying wiring intervals and wiring widths of vertical and horizontal wiring and slanted wiring mixed in the wiring graphic data.
2. Description of the Related Arts
Traditionally, in computer-aided large scale semiconductor integrated circuits design work, a location of devices is determined on the integrated circuit according to a logic circuit diagram or an electronic circuit diagram referred to as a wiring location design of a layout design, and after wiring paths between these devices are determined, a plotting operation for generating mask based on this is performed.
As is well known, in layout design, layout verification is performed. This layout verification is to confirm accuracy of design of plot data (artwork data) for generating mask in final design stage.
In this layout verification, the verification called design rule check (DRC) is performed. This is an operation which verifies that the plot data does not violate geometrical design rules which is designed with various constraint obtained after examining fabrication processes, or the design rules.
In conventional design rule check, it is verified that intervals between wiring graphics and wiring widths do not violate the design rules. In verification of intervals between wiring graphics, verification reference values vary according to the wiring widths. Also, acceptable minimum wiring width and maximum wiring width are defined for each wiring layer.
In verification of wiring intervals targeting the conventional vertical and horizontal wiring, there are a method that extracts wiring graphics which are to be verification targets and checks intervals between the wiring graphics and a method that extracts edges between wirings which are to be verification targets and checks intervals between these edges. Also, for verification of wiring widths, there are a method that extracts wiring graphics which are to be verification targets and checks widths between the wiring graphics and a method that extracts edges between wirings which are to be verification targets and checks intervals between these edges (See Japanese Patent Application Laid-open Pub. Nos. 2001-13673, Hei8-55140 and Hei11-96200).
By the way, in conventional layout design, wiring patterns are arranged in horizontal and vertical directions, but in recent years, slanted wiring in which wiring patterns are arranged in 45 degrees slanted direction has been introduced in order to shorten wiring paths, reduce line resistance and stray capacitance and improve transmission properties associated with higher frequency.
However, in verification of the layout design in case that the vertical and horizontal wiring and the slanted wiring are mixed, if the design reference values for the wiring intervals of the vertical and horizontal wiring and the slanted wiring are different respectively and also if the design reference values for minimum wiring widths and maximum wiring widths of the vertical and horizontal wiring and the slanted wiring are different respectively, then a problem occurs, in which so-called pseudo-errors, which is output as error even when it is not error, is generated by mutual interferences of different design reference values.
In other words, if layout verification is performed according to the design reference value of the vertical and horizontal wiring, the design reference value of the vertical and horizontal wiring is also applied to the slanted wiring and the pseudo-errors is generated. Conversely, if layout verification is performed according to the design reference value of the slanted wiring, the design reference value of the slanted wiring is also applied to the vertical and horizontal wiring and the pseudo-errors is generated.
Therefore, layout verification can not accommodate the layout verification in which the design reference values of the vertical and horizontal wiring and the slanted wiring are different, and different design reference values can not be applied to the vertical and horizontal wiring and the slanted wiring, so the problem occurs, in which the degree of freedom of the layout design is limited.